1. Field of the Invention
The invention relates to a computer system which comprises a primary processor station and a first random access read-write memory having a first address space interconnected by a primary bus for data, address and control signals; which furthermore comprises a second random access read-write memory having a second address space outside of said first address space, and at least one first peripheral apparatus interconnected by a secondary bus for data, address and control signals; which furthermore comprsies a coupler having a first and a second interfacing circuit for interfacing to said secondary bus, said coupler having a closed state for allowing coexistent primary bus requests on the primary bus and data transfer between respective stations connected to the secondary bus, said coupler having an open state for exchange of data characteris, addresses, data request signals and data acknowledge signals between said primary bus and said secondary bus.
2. Description of the Prior Art
A computer system of this kind is known from U.S. Pat. No. 4,257,099 to D.R. Appelt. The known system deal with a communication bus coupler for a so-called polysystem. Each element of a polysystem is comprised of a multiprocessor system with a plurality of master stations and a plurality of slave stations. Therefore, the level of cooperation in the couplers of the known system is high and the complexity thereof is great. The known system offers a solution when the system is bus through put limited and allows selective communication among various stations across the couplers or within the local system. The present invention is directed to the problem that occurs when the capacity of the bus is temporarily taken up fully by interperipheral or memory/peripheral transports. On the one hand, such transports may have a fast data throughout. On the other hand, the necessary control may be of limited extent, so that no processor station is always required to monitor this transport.